Semiconductor devices are typically fabricated by forming a number of layers of material over a wafer and etching such layers to form integrated circuitry features such as conductive lines, resistors, capacitors, interconnect lines, contact openings, and the like. Alignment of overlying layers to underlying layers can be critical, especially as device dimensions continue to shrink.
One approach which has been taken in the past to check wafer alignment during fabrication has been through the use of vernier pattern technology. This technology typically uses patterns comprising a plurality of alignment marks which are formed over one another at different wafer elevations and at different pitches. Misalignments are determined by perceived changes in the overlapping relationship of the patterns from a known overlapping relationship, and quantified by observing the extent to which the patterns' pitch variations cause the patterns to be misaligned. Additional information on alignment technologies can be found in the following references, the disclosures of which are incorporated herein: U.S. Pat. Nos. 4,610,940, 4,742,233, 5,017,514, 5,271,798, 5,545,593, 5,614,446, 5,614,767, 5,633,505, 5,637,186, 5,668,042, and 5,712,063.
This invention arose out of concerns associated with improving the methods and apparatus which are utilized to calculate alignment of layers during semiconductor processing.